Power arrays of high voltage devices are commonly used in dc-dc converters. These high voltage devices are, for instance, implemented as Lateral DMOS (LDMOS) (which is a self-aligned device implemented in a BiCMOS process) or as drain-extended MOS (DeMOS) (which is a non-self-aligned device implemented in a CMOS process). FIG. 1 shows a cross section through a typical N-LDMOS-SCR 100, which broadly speaking comprises an LDMOS having a p+ region 102 with contact 103 to provide for double injection of charge carriers. The device 100 also includes an n+ drain 104 with an extended drain region 106 in the form of an n-drift region. As is evident from FIG. 1, the drain 104 is formed in the n-drift 106, which, in turn is formed in an n-epitaxial region 110. However a p-well 112 is also formed in the n-epi 110 with the result that the n-drift 106 extends into the p-well 112. The device 100 further includes an n+ source 114 formed in a p-body 116, which is formed in the p-well 112. The p+ region 102 is, in turn, formed in a p-field region 120 that is formed in the p-body 116. A polysilicon gate 122 is provided between the drain contact 130 and source contact 132, this region between the contacts defining the active region. The poly gate 122 is separated from the silicon by an oxide layer 124, and a poly section 126 extends over the n-drift 106, being isolated from the n-drift 106 by the oxide 124.
For a better appreciation of the layout of the drain, source and gate, and especially the drain, source and gate contacts, FIG. 2 shows the NLDMOS-SCR in plan view.
It will be appreciated that in all of these extended drain devices a small footprint and good switching characteristics are an important consideration.
However, in both LDMOS and DeMOS arrays, the topology involves multiple fingers with the gates connected at the sides of the array outside the active region. In the case of non-silicided processes this creates a distributed capacitive-resistive network which negatively impacts the switching characteristics. Also, the gate connection area (indicated in FIG. 2 by reference numeral 200) requires additional space.